The present invention relates in general to logic analyzers and in particular to an apparatus for monitoring the control lines of a computer processor, determining the type of transaction being performed by the processor, and generating appropriate signals for controlling data acquisition by the logic analyzer.
A typical function of a logic analyzer is to monitor the address and data busses and the control lines appearing on the pins of a microprocessor chip and to display on a screen the sequential history of the microprocessor operation including the states of the control lines and of the lines of the address and data busses of the processor. Logic analyzers typically access the address, data and control lines of the processor by means of a probe inserted between the microprocessor and its socket in the system under test. The probe typically comprises a set of probe pins matching the microprocessor pin arrangement and a probe socket into which the microprocessor can be inserted. Internal probe wiring connects the pins of the microprocessor inserted into the probe socket to the appropriate probe pins inserted into the mother board. This allows the address, data and control lines to be brought out to buffers which can transmit the data thereon to the logic analyzer circuits.
The data acquisition portion of a logic analyzer typically stores data regarding each microprocessor transaction (such as a read or write cycle or an interrupt) in a random access acquisition memory, with data representing successive transactions being stored sequentially at successive addresses. Since the states of data and address busses of a microprocessor are only valid for a portion of a transaction cycle, a transaction analyzer must be provided to monitor selected control lines of a microprocessor and to determine when a valid transaction has occurred and to generate a write strobe signal to the acquisition memory to cause it to store the current data on the data, address and control lines of the processor.
In the prior art, most of the data acquisition portion of a logic analyzer, including the probe, the transaction analyzer and other components were specifically designed for use with only one type of microprocessor. A separate data acquisition unit must be provided for each type of microprocessor to be tested because different microprocessors have different pin arrangements, different types of control lines, different types of transactions and different timing requiremts. In copending patent application Ser. No. 801,450 filed Nov. 25, 1985 by Bogardus et al entitled "Retargetable Buffer Probe" a retargetable probe is disclosed wherein the pin and socket portion of the probe may be replaced to accomodate different types of microprocessors. A cross-connect circuit is also replaceable to allow control, data and address lines leading to the rest of the acquisition unit to appear in the same general arrangement regardless of the type of microprocessor being tested. What is needed and would be useful is a transaction analyzer for use with such a probe, which would accomodate a number of different types of microprocessors without a change in hardware.